A typical processor fetches or otherwise receives instructions from an external memory for subsequent execution or otherwise processing thereof. In general, instruction execution involves an address operation and/or a data operation, wherein the address operation produces an address value, typically, an address for a location in a memory, and the data operation produces a data value. Most instructions specify operations to be performed using one or more operands. An operand may be specified using one of several different types of addressing modes and may be included in the instructions themselves, or reside in either a register in the processor or in an external memory coupled to the processor.
Many modern processors employ a technique called pipelining to execute more software program instructions (instructions) per unit of time. In general, processor execution of an instruction involves fetching the instruction (e.g., from a memory system), decoding the instruction, obtaining needed operands, using the operands to perform an operation specified by the instruction, and saving a result. In a pipelined processor, the various steps of instruction execution are performed by independent units of the processor commonly referred to as pipeline stages. In the pipeline stages, corresponding steps of instruction execution are performed on different instructions independently, and intermediate results are passed to successive pipeline stages. By permitting the processor to overlap the executions of multiple instructions, pipelining allows the processor to execute more instructions per unit of time.
In general, a “scalar” processor issues instructions for execution one at a time while a “superscalar” processor is capable of issuing multiple instructions for execution at the same time. A pipelined scalar processor concurrently executes multiple instructions in different pipeline stages; the executions of the multiple instructions being overlapped in the manner described above. A pipelined superscalar processor, on the other hand, concurrently executes multiple instructions in different pipeline stages, and is also capable of concurrently executing multiple instructions in the same pipeline stage. Examples of pipelined superscalar processors include the popular Intel® Pentium® processors (Intel Corporation, Santa Clara, Calif.) and IBM® PowerPC® processors (IBM Corporation, White Plains, N.Y.).
A superscalar processor requires the grouping of multiple instructions to determine which instructions can be issued concurrently for execution at the same time. This grouping of multiple instructions increases the complexity of the grouping hardware required in the above-described processor. In a superscalar processor, the grouping of multiple instructions may be implemented by annotating grouping information into the instruction stream. Currently there are two techniques for annotating grouping information, the first known as a “grouping-bit annotation” technique and the second being known as an “end-of-group annotation” technique. The grouping-bit annotation technique reserves a bit in every instruction to mark that instruction as the end of the group. Because it reserves a bit in every instruction to denote whether or not that instruction is the end of a group, the grouping bit annotation technique makes instruction encodings less efficient. Conversely, the shortcoming of the end of group annotation technique is that the technique adds an extra instruction to each group of instructions to denote the end of that group. It would therefore be beneficial to provide an alternative way to annotate the grouping of multiple instructions in a superscalar processor without either reserving a bit within each instruction or adding additional instructions to the instruction stream.